(164l) Annealing Effects on the Band Alignment of ALD SiO2 on (InxGa1-x)2O3 for x = 0.25 - 0.74

There is growing interest in the development of Ga₂O₃-based heterostructures for power electronics and solar-blind UV photodetectors. Additionally, the band gap of Ga₂O_­3 can be tuned to fit a large variety of device applications by incorporating Indium during the crystal growth process. For (In_xGa_1-x)₂O₃, various growth methods have been reported, such as pulsed laser deposition (PLD), sputtering, molecular beam epitaxy, organic chemical vapor deposition, and sol-gel processing. Most of the previous research has focused on native defect behavior, miscibility gaps, and crystal phase structure as the cubic phase of In₂O₃ is alloyed with monoclinic Ga₂O₃. In device applications, the (In_xGa_1-x)₂O₃ layers can be used as channels in heterostructure transistors and to tune the wavelength response of photodetectors.

To realize these types of heterostructure devices, thin dielectric layers can be deposited prior to gate formation to form a metal-oxide-semiconductor (MOS) structure. There are many possible dielectrics one can choose, however, the dielectric’s band gap must be large enough such that it offsets the (In_xGa_1-x)₂O₃ by ideally >1 eV on both the conduction band and valence band. Atomic layer deposited SiO₂ is one of the most common dielectrics for these applications due to its large band gap and well-established deposition conditions. During the formation of Ohmic contacts or annealing of implant isolation regions in MOS transistors based on (In_xGa_1-x)₂O₃, it is necessary to anneal at temperatures of 500-600°C. There has, as of yet, been no examination of how high temperatures affect the band offsets between SiO₂ and (In_xGa_1-x)₂O₃, which is a crucial precluding step of commercializing these types of devices.

In this study, the band alignment of Atomic Layer Deposited SiO₂ on (In_xGa_1-x)₂O₃ at varying indium concentrations is reported before and after annealing at 450°C and 600°C to simulate potential processing steps during device fabrication and to determine the thermal stability of MOS structures in high-temperature applications. At all indium concentrations studied, the valence band offsets (VBO) showed a nearly constant decrease as a result of 450°C annealing. The decrease in VBO was -0.35 eV for (In_0.25Ga_0.75)₂O₃, -0.45 eV for (In_0.42Ga_0.58)₂O₃, -0.40 eV for (In_0.60Ga_0.40)₂O₃, and -0.35 eV (In_0.74Ga_0.26)₂O₃ for 450°C annealing. After annealing at 600°C, the band alignment remained stable, with < 0.1 eV changes for all structures examined, compared to the offsets after the 450°C anneal. The band offset shifts after annealing are likely due to changes in bonding at the heterointerface. Even after annealing up to 600°C, the band alignment remains type I (nested gap) for all indium compositions of (In_xGa_1-x)₂O₃ studied. Despite the shift in the offset, the confinement is still type I and greater than 1 eV for all compositions studied. These offsets allow for good carrier confinement at all compositions of (In_xGa_1−x)₂O₃ and reinforce the acceptable thermal stability of SiO₂ as a potential dielectric for this material system.