(158d) DFT Study of ALD Nucleation of Sub-Nanometer Scale Dielectric Formation on Tiopc/Graphene for Low Power Electronics Beyond CMOS

DFT Study of ALD
Nucleation of Sub-nanometer Scale Dielectric Formation on TiOPc/Graphene for
Low Power Electronics Beyond CMOS

Pabitra Choudhury^±, Jun Hong. Park^? and Andrew C. Kummel^?.

±Department
of Chemical Engineering, New Mexico Tech, Socorro, NM

?Materials
Science & Engineering Program, University of California, San Diego, CA

?Departments
of Chemistry & Biochemistry, University of California, San Diego, CA

Abstract

High performance tunneling
Field Effect Transistors (TFET) will enable next generation terahertz detectors
and new RF systems, but their realization at the nano-scale with high operation
frequency has been a challenge because the processing of III-V materials is not only incompatible with
Si CMOS technology causing high power consumption but also the cost is very
high.  So, beyond-CMOS devices, such as MOSFET devices based on 2D semiconductor
heterostuctures could be used to address some of the above mentioned
challenges.  Graphene, an atomically-thin
layer of carbon atoms, has opened many opportunities in the field of
electronics due to its tunable enhanced electronic transport properties.  Moreover,
graphene based 2D materials can provide
ballistic transport of charge carriers as well as carrier confinement, can lead
to reduce power consumption, which are essentially attractive features for
future electronic devices.  These devices require deposition of thin
dielectrics between two semiconducting layers.  It is however possible to
overcome this difficulty via ALD process.  These materials have been
made from functionalized graphene.  Initially, graphene was functionalized with
ordered monolayer and/or multi-layers of titanyl phthalocyanines (TiOPc) via
ALD process, and then the functionalized graphene was utilized to make a
Graphene/MPc/insulator sandwich, which is the essential key materials for low
power electronic devices.  We have used combined density functional theory
(DFT) calculations and experimental approach to develop this material.  Our calculations
show that upon deposition of MPc mono-/bi-layer on graphene surface does not
perturb the Dirac cone.  This could led us to design beyond CMOS electronic
devices which need to have ballistic charge transport characteristics, which
will essentially have very important applications to design low power future
electronic devices, will also be discussed.

Acknowledgement:

DFT
calculation work was also supported from NSF TeraGrid (XSEDE) resources under
allocation number [TG-DMR140131]. Use of the Center for Nanoscale Materials was
supported by the US Department of Energy, Office of Science, Office of Basic
Energy Sciences, under Contract No. DE-AC02-06CH11357.