(316g) Mechanism of Direct Growth of Graphene on Si-Based Dielectric Substrates Via Cu Grain Boundaries

Graphene, a one atom thick sheet of carbon atom in a hexagonal network â?? possesses an extraordinary combination of properties including ultra-high carrier-mobility, ultra-high thermal conductivity, ultra-fast photodetection, ultra-high sensitivity, tunable spintronics, strong/tunable optical absorption, carrier controlled interband/optical-transition, and quantum interference. To incorporate it into the semiconductor industry, most of the recent techniques rely on producing graphene on metal catalyst surfaces, which requires further transfer to desired dielectric substrates for characterizations and applications. Direct growth of wafer scale, high-quality, and monolayer graphene on silicon-based dielectrics (SiO₂/Si and Si₃N₄/Si) is critical for the next step towards realizing graphene electronics. In this talk, we will show a complete mechanism of graphene synthesis at the interface of thin copper (Cu) film and SiO₂/Si or Si₃N₄/Si dielectrics via low pressure chemical vapor deposition (LPCVD). Further, we will discuss the role of kinetics, and process parameters (temperature, CH₄/H₂ flow rate, and total pressure) in the formation of a uniform, continuous, and large-area thin graphene film on the desired dielectric surfaces. Raman spectroscopy, selective area electron diffraction (SAED), and atomic force microscope (AFM) are employed for grapheneâ?? growth rate, continuity, and structural characterizations. The Raman D-peak, G-peak, and 2D-peak occur at characteristic ~1350 cm^-1, ~1600 cm^-1, and ~2700 cm^-1 respectively. The I_D/I_G ratio (~ 0.25 ) corresponds to a graphene crystalline sp² domain size of 17 nm. The I_2D/I_G ratio (~1.4) and SAED intensity profile confirms the possible formation of graphene monolayer with the optimized conditions. The XPS shows the presence of C=C bonding at 284.5 eV, further confirming the formation of graphene. The electrical transport properties of the produced graphene will also be presented. We envision that this work will advance the high-quality growth of high-quality wafer sized graphene on silicon-based insulating substrates without the need of post-synthesis graphene transfer processes.