(562d) Pulse Dynamics of Electric Double Layer on Graphene FETs

Electric double layer (EDL) gating is a powerful tool for exploring transport in two-dimensional (2D) materials. Mobile anions and cations in an electrolyte are drifted by field-effect to the surface of a semiconducting channel and image charges are induced. The resulting sheet carrier densities are large (~10¹³-10¹⁴ cm^-2), and if this amount of reconfigurable doping could be achieved over fast (ps - ms) timescales at the device level, then novel device functionalities could be enabled for memory, security and computing. To understand the fundamental limits to EDL formation/dissipation times, the EDL dynamics are measured and simulated in response to a pulsed electric field. The timescale of the experiments is μs to ms, while the simulation is ps to ns. Experimentally, EDL dynamics are measured on graphene field-effect transistors with polyethylene oxide (PEO):CsClO₄ as the polymer electrolyte. Voltage pulses corresponding to an applied electric field of 2.3 mV/nm can be applied for 1 ms, driving the formation of EDL on the timescale of µs at room temperature and inducing sheet carrier density in the order of 10¹³ cm^-2 while avoiding electrochemistry. MD simulations show that the EDL response can be shortened to ps by increasing the applied electric field to V/nm. Within this higher electric field, the EDL formation speed is no longer linearly dependent on field strength, but becomes exponentially dependent, indicating nonlinear transport within the electrolyte. Simulation show that charge density up to 6 x 10¹³ cm^-2 can be induced within 3 ns under electric field of 1.8 V/nm. In combination, the experimental and modeling results show that the EDL response speed can be tuned by 9 orders of magnitude by tuning the electric field strength by 3 orders of magnitude. The field strength can be adjusted by miniaturization of device geometry, and the dynamics can also be further tuned by modifications to the polymer electrolyte. The results suggest that EDL gates could potentially be used as an active device component in devices with speed requirements on the timescale of nanoseconds.

This work was supported in part by NSF-DMR-EPM under Grant No. 1607935, and by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.