(662g) Molecularly Thin All-Solid-State Non-Volatile Memory Gated By a Monolayer Electrolyte
AIChE Annual Meeting
2019
2019 AIChE Annual Meeting
Materials Engineering and Sciences Division
Synthesis and Characterization of Materials for Optical and Electronic Applications
Thursday, November 14, 2019 - 10:00am to 10:20am
A non-volatile, solid-state, one-transistor (1T) memory is demonstrated based on electric double layer (EDL) gating of a WSe2 field-effect transistor (FET) using an electrolyte that is a single molecular layer thick. The âmonolayer electrolyteâ consists of cobalt crown ether phthalocyanine and lithium ions, which are positioned by field-effect at either the surface of the WSe2 channel or a h-BN capping layer to achieve â1â or â0â, respectively. Bistability is significantly improved by the h-BN cap, with density functional theory (DFT) calculations showing an enhanced trapping of Li+ near h-BN due to an adsorption energy increase of 1.345 eV compared to vacuum. The threshold voltage shift between the two states corresponds to a change in sheet carrier density of ~ 2.5 Ã 1012 cm-2, and an on-off ratio exceeding 104 at the back gate voltage of 0 V. The on-off ratio remains stable after 1000 cycles and the retention time for each state exceeds 6 hours (max measured). When the write time approaches 1 ms, the on-off ratio remains > 102, showing that monolayer electrolyte-gated, 2D non-volatile FET can respond on timescales similar to existing flash memory. The data suggest that faster switching times, and lowing switching voltages will be achievable by top gating the device â work that is currently in progress.
This research is supported by the NSF under Grant No. ECCS-GOALI-1408425 and DMR-EPM(CAREER)- 1847808